The present invention relates to loop filters used in phase locked loop (PLL) circuits.
A phase locked loop (PLL) is an electronic circuit that causes a particular system to track with a particular signal or circuit output. More specifically, a phase lock loop circuit generates periodic signals that have the same phase and frequency as a reference signal.
A PLL circuit of the prior art is shown in FIG. 4. Phase detector (PD) 14 compares a reference clock 12, such as, for example, a frequency synthesizer circuit, with a clock signal 30 generated by a voltage controlled oscillator (VCO) 28 and issues either an up pulse signal 16 or a down pulse signal 18, depending on whether the VCO 28 generated clock signal is leading or lagging the reference signal. The duration of the pulses corresponds to the magnitude of the differences. The charge pump 20 takes the up signals 16 and down signals 18 from the PD 14 and merges them into a bipolar pulse signal 22. The output signal 22 from the charge pump 20 contains a desirable DC component that is proportional to the phase difference between the VCO 28 generated clock signal 30 and the reference signal 12 and a series of AC components that contain undesirable noise. It is the duty of the loop filter 24 to eliminate the AC noise and to deliver a smooth voltage control signal 26 to the VCO 28. When the VCO 28 receives the voltage control signal 26, it adjusts the frequency of its output clock signal 30 accordingly so as to minimize the phase difference. While the PLL is in operation, this feedback process ensures that the clock signal from VCO 30 tracks the reference signal 12.
Conventionally, a loop filter used in a PLL circuit is either a passive or an active filter. U.S. Pat. No. 9,283,971 discloses a passive loop filter, which functions to short circuit pulses from the charge pump 20 to ground, to prevent them from appearing at the output. Such a type of passive loop filter, consisting of only passive elements such as resistors and capacitors, is inexpensive and simple to implement. However, modern PLL designers favor the use of active filters rather than the passive filters because active filters offer an additional benefit: an amplification of the input signal. The amplification is made possible by an operational amplifier employed in the active filter. As a result, the charge pump 20 only generates signals whose dynamic range is a fraction of the full dynamic range required by the VCO 28. This reduces the complexity of the charge pump 20 and minimizes the current mismatch of the charge pump circuit.
FIG. 5 shows an active filter disclosed in an article entitled xe2x80x9cA 1.4 GHz Differential Low-Noise CMOS Frequency Synthesizer Using a Wideband PLL Applicationxe2x80x9d that appeared in the year 2000 issue of Proceeding of International Journal of Solid State Circuit. The active filter is composed of an operational amplifier 46, a resistor 40, and a first 42 and second 44 capacitors. An input 48 feeds into the inverting input of the operational amplifier 46 while the non-inverting input of the operational amplifier is connected to AC ground 47. The output 49 of the operational amplifier 46 feeds back to the inverting input through two pathways in a parallel fashion: one through the first capacitor 42 and the resistor 40 connected in series and the other through the second capacitor 44.
Nevertheless, there are two shortcomings associated with the active filters of the prior art. Firstly, the resulting transfer function of a typical active filter, such as the filter shown in FIG. 5, has poles and zeros that are interrelated, as illustrated in the following transfer function equations:                                           V            o                    I                =                  -                                    (                              1                +                                  s                  ⁢                                      xe2x80x83                                    ⁢                                      C                    1                                    ⁢                  R                                            )                                                      s                ⁡                                  (                                                            C                      1                                        +                                          C                      2                                                        )                                            ⁢                              xe2x80x83                            [                              1                +                                  s                  ⁢                                      xe2x80x83                                    ⁢                                      (                                                                                            C                          1                                                ⁢                                                  C                          2                                                                                                                      C                          1                                                +                                                  C                          2                                                                                      )                                    ⁢                                      xe2x80x83                                    ⁢                  R                                            ]                                                          (        1        )            
Transfer Function of the active filter shown in FIG. 6.                               s          z                =                  -                      1                                          C                1                            ⁢              R                                                          (        2        )            
Transmission Zero (Transfer Function Zero) derived from equation 1.                               s          p                =                  -                      xe2x80x83                    ⁢                      1                                          (                                                                            C                      1                                        ⁢                                          C                      2                                                                                                  C                      1                                        +                                          C                      2                                                                      )                            ⁢                              xe2x80x83                            ⁢              R                                                          (        3        )            
Natural Frequency (Transfer Function Pole) derived from equation 1.
In equation 2, the value of sz is determined by the resistor R 40 and the first capacitor C1 42, both of which are also present in the formula for sp in equation 3. Consequently, it is impossible for a PLL designer to change the value of sz without changing the value of sp. This cross-interfering relationship is undesirable because the values of sz and sp have a direct influence on the shape of a filter""s frequency response profilexe2x80x94they dictate the values of fz 50 and fp 52, which are inflection points of the filter frequency response shown in FIG. 6.
The band of frequencies between fz 50 and fp 52, known as unity gain frequency band 54, are of special interest to PLL circuit designers: a stable PLL can be obtained much more readily when the designer can manipulate the unity gain bandwidth 54 freely. With an active filter like the one depicted in FIG. 5, it is not easy for the PLL designer to come up with a highly stable PLL circuit. Accordingly, it is an objective of the present invention to improve loop filter design in a way such that the poles and zeros of the resulting transfer function can be manipulated freely, without cross interference.
Another shortcoming of a typical active filter of the prior art is that it is not immune to noise introduced by power supply and ground. Such interference is undesirable because it makes a PLL circuit less stable. Accordingly, another objective of the present invention is to provide a loop filter that can eliminate common mode noise from power supply and ground.
The above objectives have been met with a new type of loop filter, situated between a charge pump and a voltage controlled oscillator in a phase lock loop circuit, having three main components: two parallel filter modules in symmetric relation to a common mode feedback control differential comparator (CMFCDC). The filter modules perform the function of blocking off undesirable frequency from the incoming signals. Each filter module has one input port and one output port. The two input ports, one from each filter module, form a differential input pair, which are connected to the differential outputs of the charge pump. The two output ports, one from each filter module, are connected to a first and a second input port of CMFCDC, which has a total of three input ports. The third input port of the CMFCDC is connected to a reference voltage. The CMFCDC keeps the average output level of the two filter modules at the same voltage level as the reference voltage by issuing counterbalancing feedback signals to the filter modules in the event that they are not the same. Although the present invention is more complex than conventional systems, it enables the use of differential processing, which eliminates common mode noise.
The filter module of the above mentioned loop filter features two independent sets of passive elements that determine the poles and zeros of the filter. Because the present invention enables the PLL designer to adjust the values of poles and zeros of the filter independently, highly stable PLL circuit designs are readily realized.